Compression of FPGA Bit stream using modified Decode Aware Placement Algorithm
نویسندگان
چکیده
FPGA uses a promising technology for developing high-performance embedded systems. Reconfiguration systems widely uses Field Programmable Gate Arrays and configured using bitstream often loaded from memory. The Bitstream Compression and Decompression technique reduce the size of the bitstream and also limits the memory constraint. The Compression mechanism improves the access bandwidth for communication and thereby
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تاریخ انتشار 2013